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Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.

• 18 years of experience with digital logic design principles, RTL design concepts or verification methodologies and languages such as UVM and SystemVerilog.

• Experience in leading design development or functional verification team in IP development for SoCs including Power, Performance and Area characterizations and optimizations.

Preferred qualifications:

• Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.

• 10 years of experience in people management.

• Experience in leading Silicon solutions development in multimedia or security or other complex SoC integrated IPs.

• Experience in managing architecture specification to define Micro-architecture and its RTL implementation and verification through constrained random testbenches.

• Knowledge of ASIC development life-cycle: architectural specification, vendor engagement, packaging, post-silicon validation, and system integration.

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology.

• Lead and manage a team of engineers working on multimedia, security or AI accelerator design, verification and integration into SoC.

• Develop Core IP front-end designs, emphasizing on microarchitecture and Register-Transfer Level (RTL) design for the next generation CPU.

• Propose performance enhancing microarchitecture features, and work with software, architect and performance teams for trade-off studies. Communicate the pros and cons of microarchitecture enhancements.

• Deliver designs meeting Power Performance Area (PPA) goals with production quality. Be familiar with modern techniques, interpret the techniques into design constructs, and languages in order to provide guidance to and participate in the performance evaluation effort.

• Lead Verification team to ensure production of quality designs. Work with physical design and power teams to meet frequency, power, and area goals.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also https://careers.google.com/eeo/ and https://careers.google.com/jobs/dist/legal/OFCCPEEOPost.pdf If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form: https://goo.gl/forms/aBt6Pu71i1kzpLHe2.