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Job Description

Intel Silicon Photonics Product Division (SPPD) is at the forefront of silicon photonics integration and is part of The Connectivity Group which is at the heart of Intel's transformation from a PC company to a company that powers the cloud and billions of smart, connected computing-devices. Since announcing the world's first hybrid silicon laser nearly a decade ago, our team continues to lead the industry with cutting-edge technology and efficient, scalable high-volume manufacturing. Our dedication to advanced development ensures that Intel Silicon Photonics continues to drive future data center bandwidth growth with smaller form factors, co-packaging, and higher speeds from 400G today to 1.6T+ and beyond tomorrow. We are looking for great talent to accelerate this journey so if you are interested in joining our leading organization then we want to hear from you.

In this role, the Senior RF Analog IC Layout Design Engineer will be part of team contributing to Silicon Photonics Solution Group's mission to transform and lead datacenter connectivity and enable Intel's differentiation in the networking space. The individual will be lead or is a member of analog/mixed-signal layout team involved in IC Layout development, with responsibility for analog/mixed-signal cell, block and chip-level custom layouts in deep sub-micron CMOS, SiGe and BiCMOS process technologies. You will quickly ramp on the existing flow, understand the challenges, and produce the work plan. Your expertise in deep submicron technology, high-speed RF IC layout design, and teamwork skills will be highly leveraged to guide activity across the entire cross-discipline, multi-site team.

Qualifications

Responsibilities 1. Work closely with RF Designers to iterate circuit layouts to achieve performance. 2. Perform critical circuit block, subsystem and top-level layout and verification using state-of-the art tools and techniques in advanced RF node processes. 3. Manage layout workflow with other layout engineers working from geographically diverse sites. 4. Perform LVS and DRC verification checks and resolve discrepancies. 5. Run active and metal fill generation, density checks, working with designers to resolve violations. 6. Manage DRC Waivers process and drive any required enablement and tool enhancements. 7. Submit GDS to internal mask preparation team and identify and drive issues to resolution.

Minimum Qualifications The ideal candidate should have BS in Electrical Engineering or Computer Engineering 1. Minimum BS Electrical Engineering and 10 years' experience ability to work with early PDKs. 2. Minimum 5 years' highly integrated high frequency RF IC physical design and verification experience in leading edge CMOS, SiGe and BiCMOS technologies. 3. Experience with physical design and verification of high-performance RF transmitter, receiver, PLL subsystems. 4. Circuit block experience with RF PLL (VCO, dividers), CDR/SerDes, TIA/Driver, Power management 5. Expert knowledge and experience with ADS, Virtuoso and/or Mentor layout, DRC, LVS and/or parasitic extraction. 6. Experience working with design engineers to iterate layouts for optimization through PEX flow. 7. Knowledge and experience with scripting (Skill, Perl) a plus 8. Possess excellent communication skills, both oral and written. 9. Possess strong technical and analytical background with good problem-solving skills.

Preferred Qualifications 1. Deep understanding of full-chip designs including custom IO and package design. 2. Familiarity with Optical communications. 3. Experience in designing custom RF layouts for 28Gbps+ operation.

Inside this Business Group

Corporate Strategy Office is chartered to support the executive office in driving corporate initiatives, including near and long-term strategy, major cross-group decision making and ensuring cross-company alignment. To deliver to that mission, the team owns shaping, driving and synthesizing insights to directionally orient trends as well as long range strategic planning/visioning , cross company alignment and greenfield innovation. Communications are essential to drive alignment so there is a focus on communications, community and acumen development. The team is ccommitted to ensuring that Intel efforts are aligned to, and actively driving success toward the most impactful business strategies.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)

It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel’s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at https://jobs.intel.com/ and not fall prey to unscrupulous elements.

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.