Job Information
Intel DFX Micro-Architect in Folsom, California
Job Description
Do Something Wonderful!
The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people’s digital lives. Come join us and do something wonderful!
Who We Are
The Memory IP Group (MIP) within the Client Engineering Group (CEG) is looking for a DFX Micro-Architect/Designer to work on DDR/LPDDR Hard IP's. In this role you will work with an experienced Mixed Signal design team to develop DFX solutions for DDR/LPDDR PHY designs going into CPU and Networking products. You will be responsible for DFX features from product definition through design, synthesis, hardening, post-silicon enabling and High-Volume Manufacturing (HVM)
Who You Are
Responsibilities of the role include, but not limited to:
Work with Logic and Analog Architects to define HAS (High Level Architecture Spec) and MAS (Micro-Architecture Spec).
Defining DFX solutions for standard industry IP features (TAP, Boundary Scan, mbist, Scan etc.) and custom logic solutions to support debug and coverage of analog building blocks.
Working with multiple disciplines (Logic, Validation, Circuits, Structural Design, HVM) to define and debug DFX solutions to meet IP and SOC needs.
Contributing to specifications at multiple levels, including the HAS (High Level Architecture Spec) and MAS (Micro-Architecture Spec)
Implementing DFX features in RTL/System Verilog
Working with pre-Silicon Validation team to ensure full validation of DFX features
Working with Structural Design team to synthesize and close timings for DFX features.
Working with Post-Si PDE to enable DFX features, assist in debug, and drive definition of tests to address yield issues.
Qualifications
Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications :
Candidate must have a Bachelor's Degree in Electrical/Computer Engineering with 6+ years of industry experience OR Master's Degree in Electrical/Computer Engineering with 4+ years of industry experience.
Experience should be concentrated in the following areas:
Experience with Industry Standard DFX IP features/specifications (TAP, Boundary Scan, mbist, Scan etc.)
Experience with logic QA tools (Lint, CDC, Spyglass)
Experience with PHY IP design, verification, and SOC Integration on multiple products
Experience with structural design flows including Synthesis, Floor planning, and Speed path analysis
Experience with enabling and debugging Post-Silicon content for HVM
Preferred Qualifications:
Experience with analog and IO design concepts
Experience with Mixed Signal Validation
Experience with High Volume Manufacturing requirements and Test development
Familiarity with DDR/LPDDR technologies
Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.
Other Locations
US, OR, Hillsboro; US, AZ, Phoenix; US, CA, Santa Clara
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)
Annual Salary Range for jobs which could be performed in US, California: $144,501.00-$217,311.00
*Salary range dependent on a number of factors including location and experience
Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
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