Job Information
Intel Logic Design Engineer in Folsom, California
Job Description
Do Something Wonderful!
Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let’s do something wonderful together. Join us, because at Intel, we are building a better tomorrow. Want to learn more? Visit our YouTube Channel (https://www.youtube.com/c/Intel/videos) or the links below!
· Life at Intel (https://www.intel.com/content/www/us/en/jobs/life-at-intel.html)
· Diversity at Intel (https://www.intel.com/content/www/us/en/diversity/diversity-at-intel.html)
Intel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields like AI, analytics, and cloud-to-edge technology is at the heart of countless innovations. With a career at Intel, you'll have the opportunity to use technology to power major breakthroughs and create enhancements that improve our everyday quality of life. Join us and help make the future more wonderful for everyone.
Who We Are
The Memory IP Group (MIP) within the Client Engineering Group (CEG) are looking for logic design engineer to work on state-of the art DDR PHY. This team works on the design of crucial DDR PHY IPs which go into next generation Intel client products.
Who You Are
You will be working with other cross-functional teams like circuit, verification, Physical design, Post-Si Validation teams to ensure successful development of the IP.
This person will also be interacting with Firmware and SoC teams to support integration.
You will be responsible for, but not limited to:
Responsible for developing micro-architecture, RTL for these PHY Ips.
Performs logic design.
Register Transfer Level (RTL) coding, and simulation to generate cell libraries, functional units, and subsystems for inclusion in full chip designs.
Participates in the development of Architecture and Microarchitecture specifications for the Logic components.
Provides IP integration support to SoC customers and represents RTL team.
Qualifications
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering or related technical field with 2+ years' experience OR a Master's degree in in Electrical Engineering, Computer Engineering or related technical field with 1+ years' experience.
Experience in RTL, logic design.
Experience working with cross functional teams (Validation, Timing, Physical design).
Preferred Qualifications:
Experience in DDR or any other PHY IPs
Post-Si Validation support experience.
Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.
Other Locations
US, Phoenix
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)
Annual Salary Range for jobs which could be performed in US, California: $106,231.00-$159,109.00
*Salary range dependent on a number of factors including location and experience
Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
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