Job Information
Intel Analog Engineer in Hillsboro, Oregon
Job Description
As a member of the Advanced Design (AD) Library technology group in TMG DE, you will be at the forefront of designing analog collateral on leading edge Intel processes to meet density and performance scaling goals of Intel CPU and SoC products, IFS Customer Product and IP. AD serves as the design interface with the process development team working out key design process interactions for all new processes. These collaterals include ESD diodes, Power clamps, analog transistors, resistors, capacitors, thermal sensing devices, and others.
Your responsibilities will include, but are not limited to, the following:
Develop and characterize state of the art analog collateral in schematic and layout, from early PDK definition of technology and deliver the developed analog components through process maturation process in advancing PDKs.
Characterize analog collateral through all PV and RV flows.
Conduct silicon to model validation covering all technology nodes.
Work with process device and reliability stake holders to co-optimize design, process modeling and design rules.
Drive on-time library PDK release with high quality, and coordinate with the design owners and multiple stake holders in device, integration, OPC, DR, and runset for customer solutions.
#DesignEnablement
Qualifications
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
Candidate must possess a MS degree with 2+ years of experience or Ph.D. with 1+ years of experience in electrical engineering, applied physics, or related fields .
2+ years of experience in the following:
Must have two or more of the following: Physical or circuit design, device physics, power/signal integrity, and/or tool flow method (TFM).
EDA solutions for layout and schematic design and optimization.
Must have two or more of the following: Large-scale data mining, HF / RF technique, method and tool, semiconductor processes, silicon to simulation validation, TCAD modeling, extraction, reliability, process-design-kit (PDK) and foundry operations.
Preferred Qualifications:
- Thorough knowledge of statistics, numerical analysis, and mathematical modeling; proficient with coding skills in one of modern programming and scripting languages.
Inside this Business Group
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.
Other Locations
US, AZ, Phoenix; US, CA, Folsom; US, CA, Santa Clara
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)
Annual Salary Range for jobs which could be performed in US, California: $123,419.00-$185,123.00
*Salary range dependent on a number of factors including location and experience
Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
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