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Job Description

Intel's Advanced Design (AD) team resides within the Design Enablement (DE) organization which works in close collaboration with our partners in process technology, IP, and products spanning client/server and networking products.

The primary focus of AD is to guide process technology definition, and design prototypes in Intel's latest process technology, supporting Intel's internal and external design customers.

Responsibilities include but are not limited to the following:

• Develop, design and test physical layer (PHY) circuits covering wireline standards in serial, memory, die-to-die, and legacy high-voltage I/O's as well as integrating them into Intel's first technology test chips.

• Design and coordination full chip planning of Intel's first technology test chips as well as the test platforms needed for high volume learning.

• Capture of design and measurement results to guide the next generation of process technology and I/O standards based on requirements for critical wireline interfaces.

• Work closely with process and product/IP engineers to anticipate interface requirements and use design and test results to accelerate process technology and product development.

#DesignEnablement

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Candidate must possess a BS degree with 3+ years of experience or MS degree with 2+ years of experience or PhD degree with 1+ years of experience in Electrical, Computer or Electrical and Computer Engineering, or related field.

Experience in the following:

• Design and test of custom analog and mixed-signal wireline and wireless circuits in one or more of the following areas: I/Os, clock generation and distribution circuits, ADCs/DACs, inductors, transmission lines, RF and millimeter-wave circuits, regulators or references.

Preferred Qualifications:

Experience in the following:

• Experience with test chip floor planning and test plan.

• Analog design skills including specification, design and verification.

• Analyze and guide layout for advanced process technology nodes.

• Mixed signal design validation.

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Other Locations

US, AZ, Phoenix; US, CA, Folsom; US, CA, Santa Clara

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)

Annual Salary Range for jobs which could be performed in US, California: $123,419.00-$185,123.00

*Salary range dependent on a number of factors including location and experience

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.