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Job Description

About the Technology Development and Design Enablement Groups:

Technology Development (TD) is the heart and soul of Moore's Law at Intel, enabling Intel to create world-changing technology that enriches the lives of every person on earth. TD drives breakthrough research and develops next generation process/packaging technologies, while also running high volume manufacturing operations in its state-of-the-art facilities in Oregon and Arizona. The Design Enablement (DE) team in TD works closely with the technology team to maximize the value proposition of the technology for our customers thru Design Technology Co-Optimization (DTCO), delivers the Process Design Kits (PDKs) and foundational IPs (FIPs), and carries out technology lead vehicle execution for Si validation. Enablement and optimization of EDA reference flow and design flow on Intel technology play a crucial role in accomplishing DE's charter.

About the Role:

Design flow development engineer will work in a team responsible for architecting, execution, and delivery of the EDA design flow for all DTCO activities, technology lead vehicle design, IP design, and product design in TD. The design flow will be built on top of a reference flow enabled on Intel technology and released from external EDA vendors. The design flow covers all aspects of front-end and back-end design from RTL to GDS, digital and analog, design creation, verification, and signoff. The candidate must be result-oriented and capable of disciplined flow execution to meet delivery milestones in a fast-paced environment on advanced technology nodes. Prior experience in EDA tool/flow and design environment development is highly desirable. Familiarity with automated SoC design methodology and/or analog/mixed-signal design methodology is a big plus.

Candidate must exhibit written and verbal communication skills.

#DesignEnablement

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.

Minimum Qualification:

Candidate must have a MS with 3+ years of experience or PhD degree with 1+ years of experience in electrical engineering, computer engineering or related field.

Experience in the following:

• Development of EDA tools, flows and/or design environment for digital or analog designs with demonstrated programing skills.

• Digital and/or analog Silicon design and methodology.

Preferred Qualification:

Experience in the following:

• Working knowledge with major (EDA) software platforms (Synopsys, Cadence, Siemens).

• Working knowledge of all aspects of digital SoC in a product setting - floorplanning, RTL design, logic synthesis, place and route, clock tree construction, extraction and timing signoff, signal integrity analysis, layout and reliability verification, and full chip integration.

• Working knowledge of key aspects of Analog tools - schematic entry, custom layout editing, extraction, simulation, reliability, and signoff.

• Demonstrated experience in establishing and qualifying digital or analog design flow from an EDA reference flow and addressing product specific design/methodology requirements and design database management.

• Demonstrated ability to understand and interpret industry EDA trend in response to advanced node requirements, drive design flow initiatives to align.

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Other Locations

US, AZ, Phoenix; US, CA, Folsom; US, CA, Santa Clara

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)

Annual Salary Range for jobs which could be performed in US, California: $144,501.00-$217,311.00

*Salary range dependent on a number of factors including location and experience

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.