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Job Description

Conceptualizes, documents, and designs tools, flows, and methods (TFM) for use in the physical design implementation of IPs, SoCs, and the interaction/handoff/reuse between IPs and SoCs. Establishes regression flows, drives improvement in RTL to GDS flows, and creates and implements methodologies for improving robustness, power, performance, area, and timing for optimizing physical design constraints. Develops new physical design techniques through innovative scripts, checkers, flows, and other CADbased automation to simplify and expedite the design process. Analyzes retrospective data on current generation quality and efficiency gaps to identify proper incremental, evolutionary, or transformative changes to the existing physical design related TFM. Partners with physical design, circuits, CAD, RTL, tool/flow owners, and thirdparty vendor teams to continuously improve physical design methodologies and efficiencies.

Qualifications

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

• Bachelor or Master of Science degree in Electrical Engineering or Computer Engineering or related field of study.

• 5+ years of related industry experience if you have Bachelor's Degree

• 3+ years of related industry experience if you have Master's Degree

• 2+ years of Static Timing Analysis experience.

• Advanced English level

• Costa Rican unrestricted work permit.

Preferred Qualifications:

• Post graduate degree Electrical Engineering, Computer Engineering, Computer Science, or in a related field of study.

• Demonstrate experience and hands-on practical knowledge with standard-cell based VLSI design methodology and relevant industry standard EDA tools.

• Experience with Synopsys Primetime or Cadence Tempus.

• Demonstrate strong analytical and problem-solving skills through relevant experiences with ASIC/SOC design convergence.

• Demonstrate experience in scripting with Unix shell, Perl and TCL.

• Good understanding of digital design, circuits, layout with a thorough understanding of CMOS processes.

• Excellent teamwork skills including ability to work with multiple and remote groups worldwide.

• Motivated self-starter, with strong ability to work independently as well as in a team environment.

• Strong verbal and written communication skills in English.

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Inside this Business Group

The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.